CADENCE DESIGN SYSTEMS ASSURA PHYSICAL VERIFICATION Datasheet

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D ATA S H E E T
BENEFITS
• Trustedsolutionwithhundredsofusers
worldwide
• KeycomponentofVirtuosophysical
designandsimulationplatform
• Intuitiveandpowerfuldebug
environmentbasedonVirtuoso
platformacceleratescheck/reworkcycle
• SeamlessintegrationwithCadenceQRC
transistor-basedparasiticextraction
andsimulationowgivesfast,silicon-
accurateanalysis
• Advanceddesignrulecapabilities
facilitatenanometerprocesschecks
FEATURES
UNIFIED DESIGN, VERIFICATION,
AND ANALYSIS ENVIRONMENT
AssuraPhysicalVericationisanintegral
partoftheVirtuosoCustomDesign
Platform.EveryreleaseofAssuraPhysical
Vericationisowtestedwiththeother
ASSURAPHYSICALVERIFICATION
ASSURA PHYSICAL
VERIFICATION
AssuraPhysicalVericationformsa
keycomponentofthedesign,parasitic
extractionandsimulationowwithinthe
VirtuosoCustomDesignPlatform.Asa
trustedsolutionwithmanyhundredsof
usersworldwide,itenablesdesignteams
tocheck,identify,andcorrectdesignand
connectivityerrorstoachievedesignsign-
offbeforetape-out.
Thetechnologyuseshierarchical
processingandmultiprocessing
techniquestorapidlyfacilitateaccurate
identicationandcorrectionofdesign
ruleerrorsineventhemostadvanced
designs.WithitsGUI-guideddebugging
environment,AssuraPhysicalVerication
acceleratesthedebugandreworkcycle
andsoreducesoverallvericationcycle
time.AssuraPhysicalVericationprovides
thebestchoiceforfastandsilicon-
accurateanalysisofcustom,AMS,andRF
ICdesignsandIPblocks.
platformcomponents.Theresultingunied
environmentacceleratescustomdesign,
verication,analysis,andsimulation
leadingtoincreaseddesignproductivity,
chipperformance,andsiliconyield.
PERFORMANCE AND CAPACITY
AssuraPhysicalVericationuses
hierarchicalprocessingandmultiprocessor
techniquestoincreaseperformanceand
capacity.AssuraPhysicalVerication
efcientlyprocesseshighlyrepetitive
structures(suchasmemory)withits
hierarchicalprocessingtechniques.A
hierarchicaldebuggingcapabilityfurther
acceleratesthedebugcyclebecause
multipleinstancesoferrorsinthesame
hierarchyonlyhavetobecorrectedonce.
Finally,multiprocessingincreasesdesign
throughputbyleveragingcost-effective
andubiquitousmulti-CPUhardware.
Cadence
®
Assura
®
PhysicalVerication—akeycomponent
ofthedesignvericationsuiteoftoolswithintheCadence
Virtuoso
®
CustomDesignPlatform—isthephysical
vericationsolutionofchoiceforAMS/customdesigners.It
utilizeshierarchicalprocessingandmultiprocessingforfast,
efcientvericationinbothinteractiveandbatchmode.