Dell External OEMR R710 Technical Manual
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Brand: Dell
Category: Computer Hardware , Desktop , Server
Type: Technical manual
Model: Dell POWEREDGE R710 , Dell R710 - PowerEdge - 4 GB RAM
Pages: 63 (1.58 Mb)
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Dell
PowerEdge R710 Technical Guide 34
8 Chipset
8.1 Overview
The PowerEdge R710 planar incorporates the Intel
®
Xeon
®
5500 processor series chipset for I/O and
processor interfacing. This chipset is designed to support the Intel Xeon 5500 and 5600 processor
series family, QuickPath Interconnect, DDR3 memory technology, and PCI Express Generation 2. The
chipset consists of the Intel 5500 chipset I/O Hub (IOH) and ICH9.
8.1.1 Intel I/O Hub (IOH)
The planar uses the Intel 5500 chipset IOH to provide a link between the Intel Xeon processor series
5500 and 5600 processor(s) and the I/O components. The main components of the IOH consist of two
full-width QuickPath Interconnect links (one to each processor), 36 lanes of PCI Express Gen2, a x4
Direct Media Interface (DMI), and an integrated IOxAPIC.
8.1.2 IOH QuickPath Interconnect (QPI)
The QuickPath Architecture consists of serial point-to-point interconnects for the processors and the
IOH. The R710 has a total of three QuickPath Interconnect (QPI) links—one link connecting the
processors, and multiple links connecting both processors with the IOH. Each link consists of 20 lanes
(full-width) in each direction with a link speed of 6.4 GT/s. An additional lane is reserved for a
forwarded clock. Data is sent over the QPI links as packets.
The QuickPath Architecture implemented in the IOH and processors features four layers:
Physical layer—This layer consists of the actual connection between components. It supports
Polarity Inversion and Lane Reversal for optimizing component placement and routing.
Link layer—This layer is responsible for flow control and the reliable transmission of data.
Routing layer—This layer is responsible for the routing of QPI data packets.
Protocol layer—This layer is responsible for high-level protocol communications, including the
implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence
protocol.
8.1.3 IOH PCI Express
PCI Express is a serial point-to-point interconnect for I/O devices. PCIe Generation 2 doubles the
signaling bit rate of Generation 1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are
backwards-compatible with Gen1 transfer rates.
The IOH has 36 PCI Express lanes. The lanes are partitioned as two x2 PCI Express Gen2 ports and
eight x4 PCI Express Gen2 ports. The x2 ports can be combined as a x4 link; however, this x4 link
cannot be combined with any of the other x4 ports. Two neighboring x4 ports can be combined as a
x8 link, and both resulting x8 links can combine to form a x16 link.
8.1.4 Intel I/O Controller Hub 9 (ICH9)
ICH9 is a highly-integrated I/O controller, supporting the following functions:
Six x1 PCI Express Gen1 ports, with the capability of combining ports 1-4 as a x4 link
PCI Bus 32-bit Interface Rev 2.3 running at 33 MHz
Serial ATA (SATA) ports with transfer rates up to 300 MB/s (R710 supports two SATA ports for
optical devices or tape backup)
Six UHCI and two EHCI (high-speed 2.0) USB host controllers, with up to 12 USB ports (R710
uses five of these ports for internal and external use)