Cypress Semiconductor CY62147DV30 Specification Sheet

Download Specification sheet of Cypress Semiconductor CY62147DV30 Computer Hardware for Free or View it Online on All-Guides.com.

Cypress Semiconductor CY62147DV30 Specification sheet - Page 1
1
Cypress Semiconductor CY62147DV30 Specification sheet - Page 2
2
Cypress Semiconductor CY62147DV30 Specification sheet - Page 3
3
Cypress Semiconductor CY62147DV30 Specification sheet - Page 4
4
Cypress Semiconductor CY62147DV30 Specification sheet - Page 5
5
Cypress Semiconductor CY62147DV30 Specification sheet - Page 6
6
Cypress Semiconductor CY62147DV30 Specification sheet - Page 7
7
Cypress Semiconductor CY62147DV30 Specification sheet - Page 8
8
Cypress Semiconductor CY62147DV30 Specification sheet - Page 9
9
Cypress Semiconductor CY62147DV30 Specification sheet - Page 10
10
Cypress Semiconductor CY62147DV30 Specification sheet - Page 11
11
Cypress Semiconductor CY62147DV30 Specification sheet - Page 12
12
4-Mbit (256K x 16) Static RAM
CY62147DV30
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05340 Rev. *F Revised August 31, 2006
Features
Temperature Ranges
Industrial: –40°C to +85°C
Automotive-A: –40°C to +85°C
Automotive-E: –40°C to +125°C
Very high speed: 45 ns
Wide voltage range: 2.20V–3.60V
Pin-compatible with CY62147CV25, CY62147CV30, and
CY62147CV33
Ultra-low active power
Typical active current: 1.5 mA @ f = 1 MHz
Typical active current: 8 mA @ f = f
max
Ultra low standby power
Easy memory expansion with CE
, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Available in Pb-free and non Pb-free 48-ball VFBGA and
non Pb-free 44-pin TSOPII
Byte power-down feature
Functional Description
[1]
The CY62147DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE
HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O
0
through I/O
15
) are placed in a high-im-
pedance state when: deselected (CE
HIGH), outputs are dis-
abled (OE
HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE
, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing the
Write Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin
TSOPII packages.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
256K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
CE
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
Power -Down
Circuit
BHE
BLE
CE
A
10
[+] Feedback